The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, in particular, a technology effective when applied to the formation of interconnects using the dual damascene process.
In recent years, a fine-pitch interconnect forming method called damascene process is becoming a leading method in the manufacture of a miniaturized semiconductor integrated circuit device.
The damascene process involves forming a fine interconnect trench in an interlayer insulating film over a semiconductor substrate, depositing a metal film over the interlayer insulating film including the inside of this interconnect trench, removing the metal film outside the interconnect trench by chemical mechanical polishing and forming a minute embedded interconnect in the interconnect trench.
A process called “dual damascene process” is the above-described damascene process but has less steps. It involves the steps of forming, below an interconnect trench formed in an interlayer insulating film, a via hole to be connected to a lower-level interconnect and simultaneously filling a metal film in the interconnect trench and via hole to form an interconnect. A process of forming a metal plug in a via hole in advance and then forming an embedded interconnect in the interconnect trench is called single damascene process.
As a metal material for an embedded interconnect, Cu (copper) is typically employed because reliability is not impaired even by the formation of fine interconnects. When an embedded interconnect is formed in an interlayer insulating film by the damascene process, it is the common practice to make the interlayer insulating film from a low-dielectric insulating material in order to reduce the capacitance generated between two adjacent interconnects. A technology of forming an embedded interconnect in an interlayer insulating film made of a low-dielectric material by the damascene process is described, for example, in Japanese Unexamined Patent Publication No. 2004-221275 or Japanese Unexamined Patent Publication No. 2003-124307.
In Japanese Unexamined Patent Publication No. 2003-163265, disclosed is a manufacturing method of an interconnect layer by the single damascene process, which comprises using an SiCN film as an antireflective film of a resist pattern for the formation of a via hole.